Published on Sep 16, 2019
This paper investigates a novel direct digital frequency synthesizer architecture, based on piecewise linear approximation with segments of nonuniform length.
The new approach allows reducing the total number of segments with respect to the well-known uniform segmentation.
In this way the size of the coefficient ROM is also reduced with beneficial effects in terms of speed and power.
We show that the optimal nonuniform segmentation (that maximizes the spurious-free dynamic range for a given number of nonuniform segments) can be obtained as the solution of a mixed-integer linear programming problem.
Three simple, suboptimal, nonuniform segmentation schemes (which lend themselves to efficient hardware implementation) are proposed in this paper. We present also several design examples and VLSI implementation results, which demonstrate the effectiveness of the developed technique
VHDL
Simulation: ModelSim XE III 6.4b.
Synthesis: XiLinx ISE 10.1.
