Published on Sep 16, 2019
Discrete cosine transform (DCT) is a widely used tool in image and video compression applications. Recently, the high-throughput DCT designs have been adopted to fit the requirements of real-time application.
Operating the shifting and addition in parallel, an error-compensated adder-tree (ECAT) is proposed to deal with the truncation errors and to achieve low-error and high-throughput discrete cosine transform (DCT) design.
Instead of the 12 bits used in previous works, 9-bit distributed arithmetic.
DA-based DCT core with an error-compensated adder-tree (ECAT). The proposed ECAT operates shifting and addition in parallel by unrolling all the words required to be computed.
Furthermore, the error-compensated circuit alleviates the truncation error for high accuracy design. Based on low-error ECAT, the DA-precision in this work is chosen to be 9 bits instead of the traditional 12 bits.
Therefore, the hardware cost is reduced, and the speed is improved using the proposed ECAT
VHDL
Simulation: ModelSim XE III 6.4b.
Synthesis: XiLinx ISE 10.1.
