Published on Sep 16, 2019
This project aims to design a single chip VLSI architecture for implementing the JPEG BASELINE IMAGE COMPRESSION standard. The architecture exploits the principles of pipelining and parallelism to the maximum extent in order to obtain high speed
The architecture for discrete cosine transform and the entropy encoder are based on efficient algorithms designed for high speed VLSI implementation. The entire architecture can be implemented on a single VLSI chip .
Data compression is the reduction or elimination of redundancy in data representation in order to achieve savings in storage and communication costs.
Data compression techniques can be broadly classified into two categories: Losless,Lossyschemes.
In lossless methods, the exact original data can be recovered while in lossy schemes a close approximation of the original data can be obtained
VHDL
Simulation: ModelSim XE III 6.4b.
Synthesis: XiLinx ISE 10.1.
