| Removal Of High Density Salt And Pepper Noise |
| Dual Stack Method |
| Quadrature Phase Shifting key Modulator Module |
| Design of Finite Impulse Response Filter |
| Adiabatic Technique For Energy Efficient Logic Circuits Design |
| Turbo Encoder For LTE Process |
| Reconfigurable Coprocessor for Redundant Radix-4 Arithmetic |
| 4 BIT SFQ Multiplier |
| New Adaptive Weight Algorithm For Salt And Pepper Noise Removal |
| Seal Encryption On FPGA, GPU AND Multi-Core Processors |
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| Lossless Implementation Of Daubechies 8-Tap Wavelet Transform |
| Design of Control Area Network Protocol |
| Asynchronous Transfer Mode Knockout Switch |
| LFSR Based Test Generator Synthesis |
| Rotation-Based Bist With Self-Feedback |
| Operation Improvement of Indoor Robot |
| Low-Power And Area-Efficient Carry Select Adder |
| Soft-Error Tolerance and Mitigation |
| Design of 16 BIT QPSK |
| Design of 64-Bit QAM |
| Custom Floating-Point Unit Generation |
| Design of JPEG Compression Standard |
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| A Framework for Correction of Multi-Bit Soft Errors |
| Spurious-Power Suppression Technique for Multimedia/DSP Applications |
| Design of A Bus Bridge Between AHB and OCP |
| General Linear Feedback Shift Register |
| Design of 16 Point Radix-4 FFT Algorithm |
| Design and Implementation of Efficient Systolic Array Architecture |
| Exploitation of Narrow-Width Values |
| Design And Synthesis Of Programmable Logic Block |
| Fault Secure Encoder |
| Pipeline VLSI Architecture |
| 3-D Lifting-based Discrete Wavelet Transform |
| Shift-Register-Based Data Transposition |
| Design and Implementation of High Speed DDR SDRAM Controller |
| Design Of Parallel Multiplier Based On RADIX-2 Modified Booth Algorithm |
| Cyclic Redundancy Checker Generator |
| Multilayer AHB Bus Matrix |
| Novel Area-Efficient FPGA Architectures |
| Implementation of FFT/IFFT Blocks for OFDM |
| Behavioral Synthesis of Asynchronous Circuits |
| Implementation Of Guessing Game |
| Very Fast and Low Power Carry Select Adder Circuit |
| Short Range MIMO Communications |
| VLSI Progressive Coding for Wavelet-based Image Compression |
| Self-Immunity Technique to Improve Register File Integrity against Soft Errors |
| Universal Asynchronous Receiver Transmitter |
| Design Of 32 Bit RISC Processor |
| Multiplication Acceleration Through Twin Precision |
| Task Migration In Mesh NOCS |
| AMBA-Advanced High Performance Bus IP Block |
| Design of On-Chip Bus with OCP Interface |
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| Implementation Of Discrete Wavelet Transform |
| Programmable Logic Block With Mixed LUT and MACROGATE |
| Design Of Reversible Finite Field Arithmetic |
| Design Of Radix-2 Butterfly processor to prevent Overflow in The Arithmetic |
| Viterbi Decoder for High Speed Applications |
| Efficient FPGA Implementation Of Convolution |
| Low Power ALU Design By Ancient Mathematics |
| Low Power Hardware Architecture for VBSME using Pixel Truncation |
| Reliable and Cost Effective Anti-collision Technique For RFID UHF Tag |
| Carry Tree Adder |
| Power Management Of MIMO Network Interfaces On Mobile Systems |
| Floating Point Multiplier |
| 8 Bit PICCO Processor |
| High-Accuracy Fixed-Width Modified Booth Multipliers |
| DDR3 Based Lookup Circuit for High Performance Network Processing |
| Performance Analysis of Integer Wavelet Transform For Image Compression |
| ASIC Design Of Complex Multiplier |
| A Processor-In-Memory Architecture For Multimedia Compression |
| Designing Efficient Online Testable Reversible Adders |
| Lightweight High-Performance Fault Detection Scheme |
| High Performance Complex Number Multiplier Using Booth-Wallace Algorithm |
| Dual Data Rate SDRAM Controller |
| FPGA-Based Architecture For Linear And Morphological Image Filtering |
| Automatic Road Extraction Using High Resolution Satellite Images |
| Low Power Flip-Flop Using Cmos Deep Submicron Technology |
| Cordic Processor for Complex DPLL |
| Digital Base Band Processor for UWB Transceiver |
| Detecting Background Setting For Dynamic Scene |
| OFDM Transmitter and Receiver Using FPGA |
| Traffic Light Controller |
| Module To Implement I2C Interface |
| Advanced Encryption System to Improvise System Speed |
| Design of Data Encryption Standard (DES) for Data Encryption |
| Low-Complexity Sequential Searcher For Robust Symbol Synchronization In OFDM Systems |
| High Throughput DA-Based DCT With High Accuracy |
| Floating Point Vector Coprocessor |
| Dual Elevator Controller |
| Register For Phase Difference Based Logic |
| Building An AMBA AHB Compliant Memory Controller |
| Direct Digital Frequency Synthesizer |
| High-Speed Low-Power Viterbi Decoder Design For TCM Decoders |
| Design of Phelix Algorithm |
| Parallel Prefix Adders Using FPGAS |
| REED SOLMEN ENCODER |
| Rail-Passenger Information System |
| JPEG Image Compression |
| Triple Des Algoritm |
